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trimless voltage controlled amplifier data sheet ssm2018 rev. c document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or paten t rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2002 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features 117 db d ynamic r ange 0.006% t ypical thd+n (@ 1 khz, u nity g ain) 140 db g ain r ange no e xternal t rimming r equired differential i nputs complementary g ain o utputs buffered c ontrol p ort i C v c onverter o n - c hip low e xternal p arts c ount low c ost functional block dia gram figure 1. general description the ssm2018 r epresents the continuing evolution of the frey operational voltage controlled element (ovce) topology that permits flexibility in the design of high perfo rmance volume control systems. the ssm2018 is laser trimmed for gain core symmetry and offset. as a result, the ssm2018 is the first professional audio quality vca to offer trimless operation. due to careful gain core layout, the ssm2018 combines the low noise of class ab topologies with the low distortion of class a circuits to offer an unprecedented level of sonic transparency. additional features include differential inputs, a 140 db ( ? 100 db to +40 db) gain range , and a high impedance control port. the ssm2018 provides an internal current - to - voltage converter. thus , no external active components are required. this device is offered in 16 - lead , plastic dip package and guaranteed for operation over the extended industrial temperature range of ? 40 c to +85 c. ssm2018 v c g gain core 1?g v g ?i g v 1?g ?i 1?g +in ?in 00345-001
ssm2018 data sheet rev. c | page 2 of 16 table of contents features .............................................................................................. 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specificatio ns ..................................................................................... 3 electrical specifications ............................................................... 3 absolute maximum ratings ............................................................ 4 transistor count ........................................................................... 4 thermal resistance ...................................................................... 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance characteristics ............................................. 6 theory of operation ...................................................................... 10 compensating the ssm2018 ..................................................... 10 control section ........................................................................... 11 applications information .............................................................. 12 basi c vca configuration ......................................................... 12 proper operating mode for the ssm2018 .............................. 12 output drive ............................................................................... 13 upgrading ssm2018 sockets .................................................... 13 te mperature compensation of the gain constant ............... 13 digital control of the gain ....................................................... 14 supply considerations and single - supply operation ........... 14 operational voltage controlled element ................................ 14 voltage controlled panner ........................................................ 15 outline dimensions ....................................................................... 16 ordering guide .......................................................................... 16 revision history 2/13 rev. b to rev. c updated format .................................................................. universal reorganized layout ............................................................ universal changed ssm 2018 t to ssm 2018 ................................ throughout changes to table 2 and transistor count section ........................ 4 added table 4 ..................................................................................... 5 changed theory of operation of the ssm 2018 t section to theory of operation section; changes to figure 28 .................. 10 changes to control section ........................................................... 11 changed applications section to applicati ons information section, changes to basic vca configuration section ............. 12 changes to output drive section, upgrading ssm2018 sockets section, temperature compensation of the gain constant section, figure 30 , and figure 31 .................................................. 13 changes to digital control of the gain section .......................... 14 updated outline dimensions ........................................................ 16 changes to ordering guide ........................................................... 16 7/02 rev. a to rev. b deleted references to ssm 2118 t ........................................... global edits to features ................................................................................ 1 edits to g eneral d escription ........................................................... 1 deleted ssm2118t f unctional b lock d iagram ............................ 1 deleted 16 - lewad plastic dip and sol from p in c onfigurations ............................................................................ 3 edits to o rdering g uide ................................................................... 3 deleted ssm2118t typical application circuit ........................... 3 deleted tpcs ................................................................................ 7 C 8 edits to a pplications ...................................................................... 10 deleted section b asic vca configuration for the ssm 21218t ............................................................................. 11
data sheet ssm2018 rev. c | page 3 of 16 specifications e lectrical s pecifications v s = 15 v, a v = 0 db, rl = 100 k ? , f = 1 khz, 0 dbu = 0.775 v rms, simple vca application circuit with 18 k ? resistors, ? v in floating, and class ab gain core bias (rb = 150 k ? ), ? 40 c < t a < +85 c, unless otherwise noted. typical specifications apply at t a = 25 c. table 1 . parameter conditions min typ max max (e grade) unit audio performance noise v in = gnd, 20 khz bandwidth C 95 C 93 dbu headroom clip point = 1% thd + n 22 dbu total harmonic distortion plus noise 2nd and 3rd harmonics only (25 c to 85 c) a v = 0 db, v in = +10 dbu 0.006 0.020 0.01 % a v = +20 db, v in = ? 10 dbu 0.013 0.03 0.02 % a v = ? 20 db, v in = +10 dbu 0.013 0.03 0.02 % input amplifier bias current v cm = 0 v 0.25 1 a offset voltage v cm = 0 v 1 15 mv offset current v cm = 0 v 10 100 na input impedance 4 m common - mode range 13 v gain bandwidth vca configuration 0.7 mhz vcp configuration 14 mhz slew rate 5 v/ s output amplifier offset voltage v in = 0 v, v c = 4 v 1.0 15 mv output voltage swing i out = 1.5 ma positive 10 13 v negative ?10 ?14 v minimum load resistance for full output swing 9 k control port bias current 0.36 1 a input impedance 1 m gain constant device powered in socket > 60 sec ?30 mv/db gain constant temperature coefficient ?3500 ppm/c control feedthrough 0 db to C 40 db gain range 1 4 3 mv maximum gain v c = ? 1.3 v 40 mv maximum attenuation v c = 4 v 100 db power supplies supply voltage range 5 18 v supply current 11 15 ma power supply rejection ratio 80 db
ssm2018 data sheet rev. c | page 4 of 16 absolute maximum rat ings table 2 . parameter rating supply voltage dual supply 18 v input voltage v s operating temperature range ? 40 c to +85 c storage temperature ? 65 c to +150 c junction temperature (t j ) 150 c lead temperature (soldering, 60 sec) 300 c esd ratings 883 (human body) model 500 v eiaj model 100 v stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. t ransistor c ount number of transistors ssm2018 ......................................................................................... 125 thermal resistance ja is specified for worst - case conditions, that is, ja is specified for device in socket for p - d i p. table 3 . thermal resistance package type ja jc unit 16 - lead , plastic dip 76 33 c/w figure 2 . typical application circuit esd caution v in+ v in? 1 v+ 2 3 4 v out 1f 18k? 18k? 150k? 50pf 47pf 18k? 3k? 1k? 1f 1f v contro l 16 15 14 13 5 6 7 12 1 1 v? v+ 10 8 9 00345-003 ssm2018t
data sheet ssm2018 rev. c | page 5 of 16 pin configuration an d function description s figure 3. table 4 . pin function descriptions pin no. name description 1 +i 1?g positive current feedback input for v 1 - g . 2 v+ positive power supply. connect this pin directly to the positive power rail. 3 ?i g negative current feedback input for v g . 4 ?i 1?g negative current feedback input for v 1 - g . 5 comp1 compensation pin. apply a capacitor to the compx pins according to the c ompensating the ssm2018 section. 6 +in non - inverting current input. 7 ?in inverting current input. 8 comp2 compensation pin. apply a capacitor to the compx pins according to the compensating the ssm2018 section. 9 comp3 compensation pin. apply a capacitor to the compx pins according to the compensating the ssm2018 section. 10 v? negative power supply. connect this pin directly to negative power rail. 11 v c control voltage input port. apply voltage to control vca according to the control section . 12 mode operating mode pin. selects class a or class ab operation as described in the proper operating mode for the ssm2018 section. 13 gnd ground. 14 v g output voltage at gain of g. 15 bal symmetry trim input for older version. do not connect for ssm2108t operation. 16 v 1?g output voltage at gain of 1 -g. +i 1?g 1 v+ 2 ?i g 3 ?i 1?g 4 v 1?g 16 ba l 15 v g 14 gnd 13 com p 1 5 +in 6 ?in 7 mode 12 v c 1 1 v? 10 com p 2 8 com p 3 9 00345-002 ssm2018 t o p view (not to scale)
ssm2018 data sheet rev. c | page 6 of 16 typical performance characteristics figure 4. thd + n frequency (80 khz low - pass filter, for a v = 0 db, v in = 3 v rms; for a v = +20 db, v in = 0.3 v rms; for a v = ? 20 db, v in = 3 v rms) figure 5. distortion distribution figure 6. thd + n vs. amplitude (gain = 0 db, f in = 1 khz, 80 khz low - pass filter) figure 7. thd + n vs. amplitude (gain = +20 db, f in =1 khz, 80 khz low - pass filter) figure 8. thd + n vs. gain (f in = 1 khz; for C 60 db a v C 20 db, v in = 10 v rms; for 0 db a v +20 db, v in = 1 v rms) figure 9 . thd + n vs. supply voltage (a v = 0 db, v in = 1 v rms, f in = 1 khz, 80 khz low - pass filter) 0.1 0.01 0.001 20 100 1k 10k 20k frequency (hz) thd + n (%) 00345-004 a v = +20db a v = ?20db a v = 0db t a = +25c v s = 15v r f = 18k? 100 90 80 70 60 50 40 30 20 10 0 0 0.005 0.010 0.015 0.020 0.025 distortion (%) units 00345-005 t a = +25c a v = 0db 300 units v in = 10dbu v s = 15v 0.1 1 0.01 0.001 0.1 1 10 t a = +25c v s = 15v r f = 18k? 20 amplitude (v rms ) thd + n (%) 00345-006 0.1 1 0.01 0.001 10m 0.1 1 t a = +25c v s = 15v r f = 18k? 2 amplitude (v rms ) thd + n (%) 00345-007 0.1 1 0.01 0.001 ?60 ?40 ?20 0 20 40 t a = +25c v s = 15v r f = 18k? gain (db) thd + n (%) 00345-008 0.1 0.01 0.001 5 6 9 12 15 18 supply voltage (v) thd + n (%) 00345-009 t a = +25c r f = 18k?
data sheet ssm2018 rev. c | page 7 of 16 figure 10 . noise density vs. frequency (unity gain, referred to input) figure 11 . maximum output swing vs. supply voltage (thd = 1% m ax) figure 12 . maximum output swing vs. frequency (thd = 1 % m ax) figure 13 . maximum output swing vs. load resistance (thd = 1 % m ax) figure 14 . typical output offset vs. gain figure 15 . gain and phase vs. frequency 500 400 300 200 100 0 10 100 1k 10k 100k frequency (hz) noise density (nv/ hz) 00345-010 t a = +25c v s = 15v 25 20 15 10 5 0 5 10 15 20 supply voltage (v) output voltage swing (v peak ) 00345-011 t a = +25c r f = ? r l = r l = 10k? 18 15 12 9 6 3 0 1k 10k 100k frequency (hz) maximum output swing (v peak ) 00345-012 t a = +25c v s = 15v r f = ? r l = r l = 10k? 15 12 9 6 3 0 100 1k 10k 100k load resistance (?) maximum output swing (v peak ) 00345-013 t a = +25c v s = 15v r f = 18k? 100 90 80 70 60 50 40 30 20 10 0 ?80 ?60 ?40 ?20 0 20 40 gain (db) output offset (mv) 00345-014 t a = +25c v s = 15v 10 90 45 0 ?45 ?90 ?135 5 0 ?5 ?10 ?15 100 1k 10k 100k 1m frequency (hz) gain (db) phase (degrees) 00345-015 t a = +25c v s = 15v phase gain
ssm2018 data sheet rev. c | page 8 of 16 figure 16 . gain vs. frequency figure 17 . distortion vs. temperature figure 18 . output noise vs. gain (v in = gnd, 20 khz bandwidth) figure 19 . control feedthrough distribution figure 20 . control feedthrough vs. frequency figure 21 . control feedthrough vs. temperature 60 40 20 0 ?20 ?40 ?60 ?80 100 1k 10k 100k 1m 10m frequency (hz) gain (db) 00345-016 t a = +25c v s = 15v 0.06 0.05 0.04 0.03 0.02 0.01 0 ?40 ?20 0 20 40 60 80 100 temperature (c) distortion (%) 00345-017 t a = +25c v s = 15v v in = +10dbu a v = ?20db and v in = ?10dbu a v = +20db v in = 10dbu a v = 0db ?60 ?70 ?80 ?90 ?100 ?110 ?40 ?60 ?20 0 20 40 gain (db) output noise (dbu) 00345-018 t a = +25c v s = 15v 100 90 80 70 60 50 40 30 20 10 0 ?3 ?2 ?1 0 1 2 control feedthrough (mv) units 00345-019 t a = +25c 0v < v c < 1.2v freq = 0hz 300 units 0 ?20 ?40 ?60 ?80 ?100 100 1k 10k 100k frequency (hz) control feedthrough (db) 00345-020 t a = +25c v s = 15v v c = 100mv rms 3 2 1 0 ?1 ?2 ?3 ?40 ?20 0 20 40 60 80 100 temperature (c) control feedthrough (mv) 00345-021 v s = 15v 0v < v c < 1.2v freq = 0hz
data sheet ssm2018 rev. c | page 9 of 16 figure 22 . gain constant vs. temperature figure 23 . gain constant linearity vs. gain figure 24 . gain flatness vs. frequency figure 25 . cmrr vs. frequency figure 26 . slew rate vs. supply voltage figure 27 . psrr vs. frequency ?20 ?25 ?30 ?35 ?40 ?40 ?20 0 20 40 60 80 100 temperature (c) gain constant (mv/db) 00345-022 v s = 15v ?28 ?29 ?30 ?31 ?32 ?33 ?80 ?60 ?40 ?20 0 20 40 60 gain (db) gain constant (mv/db) 00345-023 t a = +25c v s = 15v 0.1 0 ?0.1 ?0.2 ?0.3 ?0.4 100 1k 10k 100k frequency (hz) gain (db) 00345-024 t a = +25c v s = 15v av = 0db v in = 100v rms 0 ?20 ?40 ?60 ?80 ?100 10 100 1k 10k 100k frequency (hz) cmrr (db) 00345-025 t a = +25c v s = 15v 15.0 12.5 10.0 7.5 5.0 2.5 0 0 5 10 15 supply voltage (v) slew rate (v/s) 00345-026 t a = +25c +slew rate ?slew rate 0 ?20 ?40 ?60 ?80 ?100 10 100 1k 10k 100k frequency (hz) psrr (db) 00345-027 t a = +25c v s = 15v +psrr ?psrr
ssm2018 data sheet rev. c | page 10 of 16 theory of operation the ssm2018 has the same internal circuitry as the original ssm2018. the detailed diagram in figure 28 shows the main components of the vca. the essence of the ssm2018 is the gain core, which comprises two differential pairs (q1Cq4). when the control voltage, v c , is adjusted, current through the gain core is steered to one side or the other of the two differential pairs. the tail current for these differential pairs is set by the mode bias of the vca (class a or ab), which is labeled as i m in the diagram. i m is then modulated by a current proportional to the input voltage, labeled i s . for a positive input voltage, more current is steered (by the splitter) to the left differential pair; the opposite is true for a negative input. to understand how the gain control works, a simple example is best. take the case of a positive control voltage on pin 11. note that the bases of q2 and q3 are connected to ground via a 200 resistor. a positive control voltage produces a positive voltage on the bases of q1 and q4. concentrating on the left-most differential pair, this raises the base voltage of q1 above that of q2. thus, more of the tail current is steered through q1 than through q2. the current from the collector of q2 flows through the external 18 k feedback resistor around amplifier a3. when this current is reduced, the output voltage is also reduced. thus, a positive control voltage results in an attenuation of the input signal, which explains why the gain constant is negative. the collector currents of q2 and q3 produce the output voltage. the output of q3 is mirrored by amplifier a1 to add to the overall output voltage. on the other hand, the collector currents of q1 and q4 are used for feedback to the differential inputs. because pins 6 and 4 are shorted together, any input voltage produces an input current which flows into pin 4. the same is true for the inverting input, which is connected to pin 1. the overall feedback ensures that the current flowing through the input resistors is balanced by the collector currents in q1 and q4. compensating the ssm2018 the ssm2018 has a network that uses an adaptive compensation scheme that adjusts the optimum compensation level for a given gain. the control voltage not only adjusts the gain core steering, it also adjusts the compensation. the ssm2018 has three compensation pins: comp1, comp2, and comp3. comp3 is normally left open. grounding this pin actually defeats the adaptive compensation circuitry, giving the vca a fixed compensation point. the only time this is desirable is when the vca has fixed feedback, such as the voltage controlled panner (vcp) circuit shown later in the data sheet. thus, for the basic vca circuit or the ovce circuit, comp3 should be left open. figure 28. detailed functional diagram 15 4 16 11 13 12 9 10 6 7 2 8 5 14 3 1 bal ?i 1?g v 1?g v c v ref gnd 1.8k ? a4 a2 a1 a3 comp 2 comp 3 comp 1 v g ?i g +i 1?g v+ v? +in ?in compensation network im 00345-029 splitter gain core ssm2018 200 ? 200 ? q3 q4 q1 1?g 1?g gg q2 mode im ? ( ) is 2 im + ( ) is 2
data sheet ssm2018 rev. c | page 11 of 16 a compensation capacitor must be added between comp1 and comp2. because the vca operates over such a wide gain range, the compensation should ideally be optimized for each gain. when the vca is in high attenu ation, there is very high loop gain, and the part needs to have high compensation. on the other hand, at high gain, the same compensation capacitor would overcompensate the part and roll off the high frequency performance. thus, the ssm2018 employs a patented adaptive compensation circuit. the compensation capacitor is miller connected between the base and collector of an internal transistor. by chan ging the gain of this transistor via the control voltage, the compensation is changed. increasing the compensation capacitor causes the frequency response and slew rate to decrease, which tends to cause high frequency distortion to increase. for the basic vca circuit, 47 pf was chosen as the optimal value. the ovce circuit described later uses a 220 pf capacitor. the reason for the increase is to compensate for the extra phase shift from the additional output amplifier used in the ovce configuration. the co mpensation capacitor can be adjusted over a practical range from 47 pf to 220 pf if desired. below 47 pf, the parts may oscillate; above 220 pf the frequency response is sig nificantly degraded. control section as noted above, the control voltage on pin 11 steers the current through the gain core transistors to set the gain. the unity gain (0 db) condition occurs at v c = 0. attenuation occurs in the vca for positive voltages (0 v to 3 v, typ), and gain occurs for negative voltage (0 v to ?1.3 v, typ). from C 1.3 v to + 3.0 v, 140 db of gain range is obtainable. the output gain formula is as follows: v out = v in e ( ?av c ) (1) the exponential term arises from the standard ebers - moll equation describing the relationship of a transistors collector current as a function of the base - emitter voltage: i c = i s e ( vbe /vt ) (2) the factor a is a function not only of v t but also the scaling due to the resistor divider of the 200 ? and 1.8 k? resistors shown in figure 2 . the resulting expression for a is as follows: a = 1/(10 v t ) , which is approximately equal to 4 at room temperature. substituting a = 4 in the above equation results in a ?28.8 mv/db control law at room temperature. the ?28.8 mv/db number is slightly different from the data sheet specification of ?30 mv/db. the difference arises from the temperature dependency of the control law. the term v t is known as the thermal voltage, and it has a direct dependency on temperatu re: v t = kt / q where k = boltzmanns constant = 1.38 e ? 23 q = electron charge = 1.6 e ? 19 t = absolute temperature in kelvin) this temperature dependency leads to the ?3500 ppm/c drift of the control law. it also means that the c ontrol law changes as the part warms up. thus, our specification for the control law states that the part has been powered up for 60 seconds. when the part is initially turned on, the temperature of the die is still at the ambient temperature (25c for exa mple), but the power dissipation causes the die to warm up. with 15 v supplies and a supply current of 11 ma, 330 mw is dissipated. this number is multiplied by ja to determine the rise in the dies temperature. in this case, the die increases from 25c to approximately 50 c. a 25 c temperature change causes a 8.25% increase in the gain constant, resulting in a gain constant of 30 mv/db. the graph in figure 22 shows how the gain constant varies over the full temperature range.
ssm2018 data sheet rev. c | page 12 of 16 applications information the ssm2018 is a trimless voltage controlled amplifier (vca) for volume control in audio systems. the ssm2018 is identical to the original ssm2018 in functionality and pinout; however, it is the first professional quality audio vca in the marketplace that does not require an external trimming potentiometer to minimize distortion. instead, the ssm2018 is laser trimmed before it is packaged to ensure the specified thd and control feedthrough performance. this has a significant savings in not only the cost of external trimming potentiometers, but also the manufacturing cost of performing the trimming optimization during production. basic vca configuration the primary application circuit for the ssm2018 is the basic vca configuration, which is shown in figure 29. this configura- tion uses differential current feedback to realize the vca. a complete description of the internal circuitry of the vca, and this configuration, is given in the theory of operation section. the ssm2018 is trimmed at the factory for operation in the basic vca configuration with class ab biasing. thus, for optimal distortion and control feedthrough performance, use the same configuration and biasing. all of the graphs for the ssm2018 in the data sheet have been measured using the circuit of figure 29. figure 29. basic vca application circuit in the simple vca configuration, the ssm2018 inputs are at a virtual ground. thus, 18 k resistors are required to convert the input voltages to input currents. the schematic also shows ac coupling capacitors. these are inserted to minimize dc offsets generated by bias current through the resistors. without the capacitors, the dc offset due to the input bias current is typically 5 mv. the input stage has the flexibility to run either inverting, noninverting, or balanced. the most common configuration is to run it in the noninverting single-ended mode. if either input is unused, the associated 18 k resistor and coupling capacitor should be removed to prevent any additional noise. the common-mode rejection in balanced mode is typically 55 db up to 1 khz, decreasing at higher frequencies as shown in figure 25. to ensure good cmrr in the balanced configuration, the input resistors must be balanced. for example, a 1% mismatch results in a cmrr of 40 db. to achieve 55 db, these resistors should have an absolute tolerance match of 0.1%. the output of the basic vca is taken from pin 14, which is the output of an internal amplifier. note that the second voltage output (pin 16) is connected to the negative supply. this is normal and actually disables that output amplifier, ensuring that it does not oscillate and cause interference problems. shorting the output to the negative supply does not cause the supply current to increase. this amplifier is only used in the ovce application explained in the operational voltage controlled element section. the control port follows a ?30 mv/db control law. the application circuit shows a 3 k and 1 k resistor divider from a control voltage. the choice of these resistors is arbitrary and could be any values to properly scale the control voltage. in fact, these resistors can be omitted if the control voltage has been properly scaled. the 1 f capacitor is in place to provide some filtering of the control signal. although the control feedthrough is trimmed at the factory, the feedthrough increases with frequency (figure 20). thus, high frequency noise can feed through and add to the noise of the vca. filtering the control signal helps minimize this noise source. proper operating mode for the ssm2018 the ssm2018 has the flexibility of operating in either class a or class ab. this is accomplished by adjusting the amount of current flowing in the gain core (i m in figure 28). the traditional trade-off between the two classes is that class a tends to have lower thd but higher noise than class ab. however, by using well matched gain core transistors, distortion compensation circuitry and laser trimming, the ssm2018 has excellent thd performance in class ab. thus, it offers the best of both worlds in having the low noise of class ab with low thd. because the ssm2018 operates optimally in class ab, the distortion trim is performed for this class. to guarantee conformance to the data sheet thd specifications, the ssm2018 must be operated in class ab. this does not mean that it can not be operated in class a, but the optimal thd trim point is different for the two classes. using class a operation results to 0.05% without trim. an external potentiometer could be added to change the trim back to its optimal point as shown in the ovce application circuit, but this adds the expense and time in adjusting a potentiometer. the class of operation is set by selecting the proper value for r b shown in figure 29. r b determines the current flowing into the mode input (pin 12). for class ab operation with 15 v supplies, r b should be 150 k. this results in a current of 95 a. for other supply voltages, adjust the value of r b such that current remains at 95 a. this current follows the formula: b cc mode r v i v)7.0( ? ? (3) the factor of 0.7 v arises from the fact that the dc bias on pin 12 is a diode drop above ground. v in+ v in? 1 v+ 2 3 4 v out 1f 18k ? 18k ? r b 150k ? 50p f 47pf 18k ? 3k ? 1k ? 1f 1f v control 16 15 14 13 5 6 7 12 11 v? v+ 10 8 9 00345-028 ssm2018t
data sheet ssm2018 rev. c | page 13 of 16 output drive the ssm2018 is buffered by an internal op amp to provide a low impedance output. this output is capable of driving to within 1.2 v of either rail at 1% distortion for a 100 k load. note that this 100 k load is in parallel with the feedback resistor of 18 k, so the effective load is 15.3 k. for better than 0.01% distortion, the output should remain about 3.5 v away from either rail as shown in figure 6. as the graph of output swing versus load resistance shows (figure 13), to maintain less than 1% distortion the output current should be limited to approximately 1.3 ma. if higher current drive is required, the output should be buffered with a high quality op amp such as the ada4897-1 or the ad797. the internal amplifiers are compensated for unity gain stability and are capable of driving a capacitive load up to 4700 pf. larger capacitive loads should be isolated from the output of the ssm2018 by the use of a 50 series resistor. figure 30. upgrading ssm2018 sockets upgrading ssm2018 sockets the ssm2018 easily replaces the ssm2018 in the basic vca configuration. the parts are pin for pin compatible allowing direct replacement. at the same time, the trimming potentiometers for symmetry and offset should be removed, as shown in figure 30. upgrading immediately to the ssm2018 saves the expense of the potentiometers and the time in production of trimming for minimum distortion and control feedthrough. if the ssm2018 is used in the ovce or vcp configuration, the ssm2018 can still directly replace it; however, the potentiometers cannot necessarily be removed, as explained in the operational voltage controlled element and voltage controlled panner sections. temperature compensa tion of the gain constant the gain constant has a ?3500 ppm/c temperature drift due to the inherent nature of the control port. over the full temperature range of ?40c to +85c, the drift causes the gain to change by 7 db if the part is in a gain of 20 db. if the application requires the gain constant to be the same over a wide temperature range, external temperature compensation should be employed. the simplest form of compensation is a temperature compensating resistor (tcr) such as the pt146 from precision resistor co. these elements are different than a standard thermistor in that they are linear over temperature to better match the linear drift of the gain constant. figure 31. two tcrs compensate for temperature drift of gain constant the gain constant has a ?3500 ppm/c temperature drift that is due to the reciprocal dependence of the design on absolute temperature. this causes the gain to vary by 7 db over the temperature range from ?40c to +85c when the nominal gain at room temperature is set to 20 db. the gain change is quite small if the temperature range of operation is restricted. nevertheless, the tc of the gain constant is easily compensated by buffering the control voltage to the vca with a circuit having a 3500 ppm/c temperature coefficient. figure 31 shows a simple solution to the problem using an op amp with a pt146 temperature compensating resistor from the precision resistor company. note that this circuit is inverting, which changes the gain constant to a positive quantity. any other circuit that provides the necessary positive tc works. v+ remove for ssm2018t 10m ? offset trim v in+ v in? 1 v+ 2 3 4 v out 1f 1f 18k ? 1k ? nc 18k ? r b 50pf 47pf 18k ? 3k ? 1f v control notes 1. r b : 150k ? for class ab. 2. nc = no connect. 16 15 14 13 5 6 7 12 11 v? v+ 10 8 9 00345-030 ssm2018 v? 500k ? 100k ? 470k ? symmetry trim control voltage 1k ? * 2k ? +15v ?15v *pt146 available from precision resistor co. 10601 75th street north largo, fl. 34647 (727) 541-5771 00345-031 op27 pin 11 ssm2108/ ssm2108t
ssm2018 data sheet rev. c | page 14 of 16 digital control of t he gain a common method of controlling the gain of a vca is to use a digital - t o - analog converter to set the control voltage. figure 32 shows a 12 - bit dac, the dac8512, controlling the ssm2018 . the dac8512 is a complete 12 - bit converter in an 8 - pin package . it includes an on - board reference and an output amplifier to produce an output voltage from 0 v to 4.095 v, which is 1 mv /bit. since the voltage is always positive, this circuit only provides attenuation. the resistor divider on the output of the dac8512 is set to scale the output voltage so that full scale produces 80 db of attenuation. the resistor divider can be adjusted to provide other attenuation ranges. if a parallel interface is needed, then the dac8562 may be used or, for a dual dac, the ad8582. figure 32 . 12 - bit dac controls the vca gain supply consideration s and single - supply operation t he ssm2018 has a wide operating supply range. many of the graphs in this data sheet show the performance of the part from 5 v to 18 v. these gra phs offer typical performance specifications and are a good indication of the parts capabilities . the minimum operating supply voltage is 4.5 v. below this voltage, the parts are inoperable. thus, to account for supply variations, the recommended minimum supply is 5 v. for simplicity , the circuits in the data sheet do not show supply decoupling; however, to ensure best performance, each supply pin should be decoupled with a 0.1 f ceramic (or other low resistanc e and inductance type) capacitor as close to the package as possible. this minimizes the chance of supply noise feeding through the part causing excessive nois e in the audio frequency range. the ssm2018 can be operated in single - supply mode as long as the circuit is properly biased. figure 33 shows the proper configuration, which includes an amplifier t o create a false ground node midway between the supplies. a high quality, wide bandwidth audio amplifier, such as the ada4897 - 1 or the ad797 , should be used to ensure a very low impedance ground over the full audio frequency range. the minimum operating supply for the ssm2018 is 5 v, which gives a minimum single - supply of +10 v and ground. the performance of the circuit with +10 v is identical to graphs that show operation of the ssm2018 with 5 v supplies. figure 33 . single - supply operation of ssm2018 operational voltage controlled element the ssm2018 has considerable flexibility beyond the basic vca circuit utilized throughout this data sheet. the name o perational v oltage c on trolled e lement (ovce) comes from the fact that the part behaves much like an operational amplifier with a second voltage controlled output. the symbol for the ovce connected as a unity gain follower/vca is shown in figure 34 . the voltage output labeled v 1 C g is fed back to the inverting input as it is for an op amps feedback. the v g output is amplified or attenuated depending upon the control voltage. because the ovce works similarly to an op amp, the feedback could as easily have included resistors to add gain, or a filter network to add frequency shaping. the full application circuit for the ovce is shown in figure 35 . not e that the amplifier whose output (pin 16) was originally connected to vminus is now the output for feedback. as mentioned before, because the ssm2018 is trimmed for the basic vca configuration, potentiometers are needed for the ovce configuration to ensure the best thd and control feedthrough performance. 1 v in 2 3 4 v out 0.1f 18k? 150k? nc nc = no connect 18k? 50pf 47pf nc nc nc 16 15 14 13 5 6 7 12 1 1 +15v 10 8 9 00345-032 ?15v +15v ssm2018t 0.1f 0.1f 0v v c +2.24v r7 1k? c con 1f +5v r6 825? dac8512 2 1 8 7 6 5 3 4 cs clr ld sclk sdi v in+ v in? 1 v+ 2 3 4 v out 1f 1f 18k? 1k? 18k? r b 50pf 47pf 10f 18k? 100k? 100k? 3k? 1f v contro l 16 15 14 13 5 6 7 12 1 1 v+ 10 8 9 00345-033 ssm2018t v+ v+ op176
data sheet ssm2018 rev. c | page 15 of 16 if a symmetry trim is to b e performed, it should precede the control feedthrough trim and be done as follows: 1. apply a 1 khz sine wave of 10 dbu to the input with the control voltage set for unity gain. 2. adjust the symmetry trim potentiometer to minimize distortion of the output sign al. next, the control feedthrough trim is done as follows: 1. ground the input signal port and apply a 60 hz sine wave to the control port. the sine wave should have its high and low peaks correspond to the highest gain to be used in the application and 30 db of attenuation, respectively. for example, a range of 20 db gain to 30 db attenuation requires that the sine wave amplitude ranges between ? 560 mv and +840 mv on pin 11. 2. adjust the control feedthrough potentiometer to null the signal seen at the output. figure 34 . ovce follower/vca connection figure 35 . ovce application circuit voltage controlled p anner an interesting circuit that is built with the ovce building block is a voltage controlled panner. figure 36 shows the feedback c onnection for the circuit. not e that the average of both outputs is fed back to the input. thus, the average must be equal to the input v oltage. when the control voltage is set for gain at v g , this causes v 1 C g to attenuate (to keep the average the same). on the other hand, when v g is attenuated, v 1 C g is amplified. the result is that the control voltage causes the input to pan from one output to the other. the following expressions show how this circuit works mathematically: v g = 2 k v in and v i ?g = 2(1 ? k) v in (4) where k varies between 0 and 1 as the control voltage is changed from full attenuation to full gain, respectively. when v c = 0, then k = 0.5 and v g = v 1 C g = v in . again, trimming is required for best performance. pin 9 must be grounded. this is possible because the feedback is constant and the adaptive network is not needed. the vcp is the only application shown in this data sheet where pin 9 is grounded. figure 36 . basic vcp connection v g v c v in v 1?g 00345-034 1 v+ + ? 2 3 4 v g v? 1f nc symmetr y trim contro l feedthrough trim 1k? 18k? notes 1. rb = 30k? for class a. 150k? for class b. 2. nc = no connec t . 470k? 18k? 10m? 500k? inputs r b v+ v? 50pf 220pf 3k? v contro l 16 15 14 13 5 6 7 12 1 1 v+ 10 8 9 00345-035 50pf v 1?g ssm2018 100k? v g v c v in v 1?g v g v c 18k? 18k? v in v 1?g 00345-036
ssm20 18 data sheet rev. c | page 16 of 16 outline dimensions figure 37 . 16 - lead plastic dual in - line package [pdip] narrow body (n - 16) dimensions shown in inches and (millimeters) ordering guide model 1 temperature range package description package option ssm2018 p z C 40 c to +85 c 16 - lead plastic dual in - line package [pdip] n -16 ssm2018t pz C 40 c to +85 c 16 - lead plastic dual in - line package [pdip ] n - 16 1 z = rohs compliant part. controlling dimensions are in inches; millimeter dimensions (in p arentheses) are rounded-off inch equi v alents for reference on l y and are not appropri a te for use in design. corner leads m a y be configured as whole or half leads. compliant t o jedec s t andards ms-001-ab 073106-b 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0. 1 15 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 16 1 8 9 0.100 (2.54) bsc 0.800 (20.32) 0.790 (20.07) 0.780 (19.81) 0.210 (5.33) max sea ting plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7. 1 1) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0. 1 15 (2.92) ? 2002 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00345 - 0 - 2/13(c)

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